FIG. 1 is a schematic block diagram of a conventional memory module system 1. Referring to FIG. 1, the memory module system 1 includes a plurality of memory modules 10, a controller 20, and a memory buffer 30.
Each of the memory modules 10 includes a plurality of memory blocks 11. The memory blocks 11 are connected to the controller 20 via respective corresponding channels CH0, CH1, CH2, and CH3. The controller 20 includes a plurality of channel controls for respectively controlling the plurality of the channels CH0, CH1, CH2, and CH3. The controller 20 outputs selection signals CS0-CH0 through CS3-CH3.
In the conventional memory module system 1, four sets of selection signals CS0-CH0 through CS3-CH3 respectively corresponding to four memory blocks 11 in each memory module must be output in order to access the memory blocks 11. For instance, in a case where four memory blocks 11 are included in each of the four memory modules 10, as shown in FIG. 1, 16 selection signals CS0-CH0 through CS3-CH3 are needed in order to access all of the memory modules 10. Accordingly, when the capacity of the memory module system 1 is increased, the number of control signals and the number of pins for transmitting and receiving the control signals are also increased. As a result, the circuit of the controller 20 becomes complicated.
FIG. 2 is a schematic block diagram of another conventional memory module system 2. Referring to FIG. 2, the memory module system 2 includes a plurality of memory modules 40, a controller 50, and a memory buffer 60.
In order to reduce the number of control signals compared to the memory module system 1 shown in FIG. 1, the memory module system 2 outputs module selection signals CS0, CS1, CS2, and CS3 only when accessing memory blocks 41 included in each of the memory modules 40.
However, when only the module selection signals CS0, CS1, CS2, and CS3 are output, the memory module system 2 needs to simultaneously access all of the memory blocks 41 included in each memory module 40. In other words, when one memory module 40 is selected, all of the memory blocks 41 included in the selected memory module 40 are simultaneously selected. As a result, the memory blocks 41 cannot be selected independently and individually.
Moreover, when there is a memory block 41 that is not connected with one of a plurality of channels CH0, CH1, CH2, and CH3, e.g., when there is an empty memory block 41, the memory module system 2 does not operate. As a result, the memory module system 2 must include as many memory blocks 41 as the number of channels in each memory module 40.
Furthermore, when the memory module system 1 or 2 shown in FIGS. 1 and 2, respectively, uses NAND flash memory modules, the controller 20 or 50 needs to control the memory module system 1 or 2 by performing wear leveling, bad block management, logical block address and physical block address management, etc.
Accordingly, when the capacity of the memory module system 1 or 2 is increased, the design of the controller 20 or 50 and software (embedded firmware) for controlling the controller 20 or 50 become more complicated. In addition, since the capacity of the memory buffer 30 or 60 connected with the controller 20 or 50 is also increased, cost for manufacturing the memory module system 1 or 2 is increased.